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1 typical a pplica t ion fea t ures descrip t ion dual 12-/10-/8-bit pwm to v out dacs with 10ppm/c reference the lt c ? 2644 is a family of dual 12-, 10-, and 8-bit pwm - to-voltage output dacs with an integrated high accuracy, low drift, 10ppm/ c reference in a 12-lead msop package. it has rail- to- rail output buffers and is guaranteed monotonic. the ltc2644 measures the period and pulse width of the pwm input signals and updates the voltage output dacs after each corresponding pwm input rising edge. the dac outputs update and settle to 12- bit accuracy within 8s typically and are capable of sourcing and sinking up to 5ma (3 v) or 10ma (5 v), eliminating voltage ripple and replacing slow analog filters and buffer amplifiers. the ltc2644 has a full-scale output of 2.5 v using the 10ppm/ c internal reference. it can operate with an external reference, which sets the full-scale output equal to the ex - ternal reference voltage. each dac enters a pin-selectable idle state when the pwm input is held unchanged for more than 60 ms. the part operates from a single 2.7v to 5.5 v supply and supports pwm input voltages from 1.71v to 5.5v. pwm input to dac output 2-channel pwm to voltage output dac a pplica t ions n digital calibration n trimming and adjustment n level setting n process control and industrial automation n instrumentation n automotive l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5396245, 5859606, 6891433, 6937178, 7414561. n no latency pwm -to-v oltage conversion n voltage output updates and settles within 8s n 100khz to 30hz pwm input frequency n 2.5lsb max inl; 1lsb max dnl (ltc2644-12) n guaranteed monotonic n pin-selectable internal or external reference n 2.7v to 5.5v supply range n 1.71 v to 5.5v input voltage range n low power: 2.7ma at 3v, <1a power-down n guaranteed operation from C40c to 125c n 12-lead msop package ltc2644 pwm inputs in a in b buffered voltage outputs gnd pd 0.1f 1.7v to 5.5v 2.7v to 5.5v iov cc v outa v outb gnd idlsel refsel ref v cc 2644 ta01a 0.1f 0.1f input: 1v to 5.5v output: 1.25v 20s/div 2644ta01b v outa 500mv/div in a 2v/div ltc 2644 2644fa for more information www.linear.com/ltc2644
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings (notes 1, 2) 1 2 3 4 5 6 v cc v outa v outb idlsel iov cc gnd 12 11 10 9 8 7 gnd refsel ref in a in b pd top view ms package 12-lead plastic msop (4mm 4.9mm) t jmax = 150c, ja = 135c/w supply voltages (v cc , iov cc ) ...................... C0. 3 v to 6v in a , in b ........................................................ C0. 3 v to 6v idlsel , pd , refsel .................................... C 0.3 v to 6v v outa , v outb ................... C0. 3 v to min (v cc + 0.3 v, 6v) ref .................................. C 0.3 v to min (v cc + 0.3 v, 6v) operating temperature range ltc 26 44 c ................................................ 0 c to 70 c ltc 26 44 i ............................................. C4 0 c to 85 c ltc 26 44 h .......................................... C 40 c to 125 c maximum junction temperature .......................... 15 0 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c ltc 2644 2644fa for more information www.linear.com/ltc2644
3 ltc2644 c ms Cl 12 #tr pbf lead free designator tape and reel tr = 2,500-piece tape and reel resolution 12 = 12-bit 10 = 10-bit 8 = 8-bit full -scale vol tage, internal reference mode l = 2.5v package type ms = 12-lead msop temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) h = automotive temperature range (C40c to 125c) product part number consult lt c marketing for parts specified with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. p ro d uc t s elec t ion g ui d e part number part marking* resolution channels vfs with internal reference maximum inl package description ltc2644-l12 ltc2644-l10 ltc2644-l8 644l12 644l10 2644l8 12-bit 10-bit 8-bit 2 2 2 2.5 v 2.5v 2.5v 2.5lsb 1lsb 0.5lsb 12- lead plastic msop 12-lead plastic msop 12-lead plastic msop * t emperature grades are identified by a label on the shipping container. o r d er i n f or m a t ion http://www .linear.com/product/ltc2644#orderinfo ltc 2644 2644fa for more information www.linear.com/ltc2644
4 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 2.5 v v psr power supply rejection v cc = 3v 10% or 5v 10% C80 db i sc short circuit output current (note 5) sinking sourcing v fs = v cc = 5.5v zero-scale; v out shorted to v cc full-scale; v out shorted to gnd l l 27 C28 48 C48 ma ma power supply v cc positive supply voltage for specified performance l 2.7 5.5 v iov cc digital input supply voltage for specified performance l 1.71 5.5 i cc supply current (note 6) v cc = 3v, internal reference v cc = 5v, internal reference l l 2.7 4.6 4 6 ma ma i cc(iovcc) supply current, iov cc (note 6) iov cc = 5v l 25 50 a i sd supply current in power-down mode (note 6) v cc = 5v, pd = 0v l 0.5 5 a i sd(iovcc) supply current in power-down mode, iov cc (note 6) iov cc = 5v, pd = 0v l 0.5 5 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. symbol parameter conditions ltc2644-l8 ltc2644-l10 ltc2644-l12 units min typ max min typ max min typ max dc performance resolution l 8 10 12 bits monotonicity v cc = 3v, internal ref. (note 3) l 8 10 12 bits dnl differential nonlinearity v cc = 3v, internal ref. (note 3) l 0.5 0.5 1 lsb inl integral nonlinearity v cc = 3v, internal ref. (note 3) l 0.05 0.5 0.2 1 1 2.5 lsb zse zero-scale error v cc = 3v, internal ref., code = 0 l 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 3v, internal ref. (note 4) l 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coefficient v cc = 3v, internal ref. (note 9) 10 10 10 v/c ge gain error v cc = 3v, internal ref. l 0.2 0.8 0.2 0.8 0.2 0.8 %fsr ge tc gain temperature coefficient v cc = 3v, internal ref. (note 9) c-grade i-grade h-grade 10 10 10 10 10 10 10 10 10 ppm/c ppm/c ppm/c load regulation internal ref., mid-scale, v cc = 3v 10%, C5ma i out 5ma l 0.009 0.016 0.035 0.064 0.14 0.256 lsb/ma v cc = 5v 10%, C10ma i out 10ma l 0.009 0.016 0.035 0.064 0.14 0.256 lsb/ma r out dc output impedance internal ref., mid-scale, v cc = 3v 10%, C5ma i out 5ma l 0.09 0.156 0.09 0.156 0.09 0.156 v cc = 5v 10%, C10ma i out 10ma l 0.09 0.156 0.09 0.156 0.09 0.156 ltc2644-l12/-l10/-l8 (v fs = 2.5v) ltc 2644 2644fa for more information www.linear.com/ltc2644
5 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. symbol parameter conditions min typ max units reference input v ref input voltage range l 1 v cc v resistance l 120 160 200 k capacitance 7.5 pf i ref reference current, power-down mode dac powered down l 0.005 1.5 a reference output output voltage l 1.24 1.25 1.26 v reference temperature coefficient (note 9) 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short circuit current v cc = 5.5v, ref shorted to gnd 2.5 ma digital inputs (in a , in b , pd) v ih digital input high voltage l 0.8?iov cc v v il digital input low voltage l 0.5 v i lk digital input leakage in a /in b = gnd to iov cc l 1 a c in digital input capacitance (note 7) l 5 pf ac performance t s settling time from in a /in b rising edge (note 8) 0.39% (1 lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 7.0 7.4 7.8 s s s voltage output slew rate 1.0 v/s capacitive load driving 500 pf glitch impulse at mid-scale t ransition 2.1 nv ? s dac-to-dac crosstalk 1 dac held at fs, 1 dac switched 0 to fs 0.9 nv ? s multiplying bandwidth external reference 320 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 180 160 200 180 nv / hz nv/hz nv/hz nv/hz output v oltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference c ref = 0.1f 35 40 680 730 nv p-p nv p-p nv p-p nv p-p ltc2644-l12/-l10/-l8 (v fs = 2.5v) ltc 2644 2644fa for more information www.linear.com/ltc2644
6 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages with respect to gnd. note 3: linearity and monotonicity are defined from code 16 to code 4095 (ltc2644-12), code 4 to code 1023 (ltc2644-10) or code 1 to code 255 (ltc2644-8). note 4: inferred from measurement at code 16 (ltc2644-12), code 4 (ltc2644-10) or code 1 (ltc2644-8), and at full-scale. note 5: this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 6: inx at 0v or iov cc . note 7: guaranteed by design and not production tested. note 8: internal reference mode. dac is stepped ? scale to ? scale and ? scale to ? scale. load is 2k in parallel with 100pf to gnd. note 9: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. symbol parameter conditions min typ max units t pwh in a /in b high time l 25 ns t pwl in a /in b low time l 25 ns t per in a /in b rising edge to rising edge period ltc2644-l12 l 0.160 33 ms ltc2644-l10 l 0.040 33 ms ltc2644-l8 l 0.010 33 ms t 3 in a /in b idle mode timeout l 50 70 ms t 4 in a /in b rising edge to dac update delay 3.2 s f max in a /in b frequency ltc2644-l12 l 0.03 6.25 khz ltc2644-l10 l 0.03 25 khz ltc2644-l8 l 0.03 100 khz ltc2644-l12/-l10/-l8 (v fs = 2.5v) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. ltc 2644 2644fa for more information www.linear.com/ltc2644
7 typical p er f or m ance c harac t eris t ics dnl vs temperature reference output voltage vs temperature settling to 1lsb rising settling to 1lsb falling integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature temperature (c) ?50 inl (lsb) 0.5 1.0 25 50 0 75 100 2644 g03 0 ?25 125 ?0.5 ?1.0 v cc = 3v inl = (pos) inl = (neg) temperature (c) ?50 dnl (lsb) 0.5 1.0 25 50 0 75 100 2644 g04 0 ?25 125 ?0.5 ?1.0 v cc = 3v dnl = (pos) dnl = (neg) (t a = 25c, unless otherwise noted.) ltc2644-12 (internal reference, v fs = 2.5v) temperature (c) ?50 v ref (v) 1.255 1.260 25 50 0 75 100 2644 g05 1.250 ?25 125 1.245 1.240 v cc = 3v 2s/div 2644 g06 in x 5v/div v outx 1lsb/div 1/4 scale to 3/4 scale step v cc = 5v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events 7s 2s/div 2644 g07 v outx 1lsb/div 3/4 scale to 1/4 scale step v cc = 5v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events 7.8s in x 5v/div duty cycle (%) 0 inl (lsb) 0.5 1.0 50 75 2644 g01 0 25 100 ?0.5 ?1.0 v cc = 3v t per = 200s internal reference duty cycle (%) 0 dnl (lsb) 0.5 1.0 50 75 2644 g02 0 25 100 ?0.5 ?1.0 v cc = 3v t per = 200s internal reference ltc 2644 2644fa for more information www.linear.com/ltc2644
8 typical p er f or m ance c harac t eris t ics integral nonlinearity (inl) ltc2644-10 (internal reference, v fs = 2.5v) ltc2644-8 (internal reference, v fs = 2.5v) ltc2644 differential nonlinearity (dnl) load regulation current limiting offset error vs temperature integral nonlinearity (inl) differential nonlinearity (dnl) 25 50 75 100 125 0?25?50 temperature (c) 2644 g14 3 2 1 0 ?1 ?2 ?3 offset error (mv) duty cycle (%) 0 inl (lsb) 0.5 1.0 50 75 2644 g08 0 25 100 ?0.5 ?1.0 v cc = 3v t per = 50s internal reference duty cycle (%) 0 dnl (lsb) 0.5 1.0 50 75 2644 g09 0 25 100 ?0.5 ?1.0 v cc = 3v t per = 50s internal reference duty cycle (%) 0 inl (lsb) 0.5 1.0 50 75 2644 g10 0 25 100 ?0.5 ?1.0 v cc = 3v t per = 10s internal reference duty cycle (%) 0 dnl (lsb) 0.5 1.0 50 75 2644 g11 0 25 100 ?0.5 ?1.0 v cc = 3v t per = 10s internal reference 0 10 20 30 ?10?20?30 i out (ma) 2644 g12 10 8 6 4 0 ?2 ?4 ?6 ?8 ?10 v cc = 5v v cc = 3v internal ref. code = mid-scale ?v out (mv) 2 0 10 20 30 ?10?20?30 i out (ma) 2644 g13 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 v cc = 5v v cc = 3v internal ref. code = mid-scale ?v out (mv) (t a = 25c, unless otherwise noted.) ltc 2644 2644fa for more information www.linear.com/ltc2644
9 typical p er f or m ance c harac t eris t ics entering idle mode full-scale from mid-scale (idlsel = gnd) exiting idle mode zero-scale to mid-scale (idlsel=gnd) exiting idle mode full-scale to mid-scale (idlsel = gnd) exiting idle mode power-down (1 channel) to mid-scale (idlsel = v cc ) power-on-reset to idle mode full-scale (idlsel = gnd) large-signal response in x to v outx delay full-scale transition entering idle mode zero-scale from mid-scale (idlsel = gnd) ( t a = 25c, unless otherwise noted.) (internal reference, v fs = 2.5v) 2s/div 2644 g15 v outx 0.5v/div v fs = v ref = v cc = 5v 1/4 scale to 3/4 scale 2s/div 2644 g16 in a 2/div v outa 500mv/div 10ms/div 2644 g17 in a 2v/div v outa 500mv/div 1ms/div 2644 g19 in a 2v/div v outa 500mv/div 500s/div 2644 g21 in a 2v/div v outa 500mv/div v ref 1v/div 10ms/div 2644 g22 v cc 2v/div in a 2v/div v outa 2v/div v ref 1v/div 10ms/div 2644 g18 in a 2v/div v outa 500mv/div 1ms/div 2644 g20 in a 2v/div v outa 500mv/div ltc 2644 2644fa for more information www.linear.com/ltc2644
10 typical p er f or m ance c harac t eris t ics multiplying bandwidth gain error vs reference input gain error vs temperature headroom at rails vs output current noise voltage vs frequency dac-to-dac crosstalk (dynamic) supply current vs input period (t per ) supply current vs duty cycle (t pw /t per ) mid-scale glitch impulse period (s) 2 i cc (ma) 3 5 7 8 10 100 10,000 100,000 2644 g23 1 1 1000 6 4 0 ltc2644-12 duty cycle = 50% 2-channels active v cc = 5v v cc = 3v 50 75 100 25 0 duty cycle (%) 2645 g24 3.00 2.75 2.50 2.25 2.00 ltc2644-12 v cc = 3v, idlsel = 0v 2-channels active i cc (ma) t per = 20ms t per = 200s 1k 10k 100k 1m frequency (hz) db 2644 g26 2 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 v cc = 5v v ref(dc) = 2v v ref(ac) = 0.2v p-p code = full scale 1 2.521.5 4 4.5 5 3 3.5 5.5 reference voltage (v) gain error (%fsr) 2644 g27 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 v cc = 5.5v gain error of 2 channels ?50 0?25 75 100 25 50 125 temperature (c) gain error (%fsr) 2644 g28 1.0 0.5 0 ?0.5 ?1.0 0 1 2 3 4 5 6 97 8 10 i out (ma) v out (v) 2644 g29 5.0 4.5 4.0 3.5 3.0 2.0 1.5 1.0 2.5 0.5 0 3v sourcing 5v sinking 3v sinking 5v sourcing 100 1k 10k 100k 1m frequency (hz) noise voltage (nv/hz) 2644 g30 500 400 300 200 100 0 v cc = 5v code = mid-scale internal ref 2s/div 2644 g31 in a 5v/div daca switch 0-fs 2v/div v outb 1mv/div ltc2644-12, v cc = 5v v ref = 2.5v 0.9nv-s typ (t a = 25c, unless otherwise noted.) (internal reference, v fs = 2.5v) 2s/div 2644 g25 v outx 5mv/div in x 5v/div ltc2644-12 v cc = 5v 2.1nv-s typical ltc 2644 2644fa for more information www.linear.com/ltc2644
11 p in func t ions v cc (pin 1): supply voltage input. 2.7v v cc 5.5v. bypass to gnd with a 0.1f capacitor. v outa , v outb (pins 2, 3): dac analog voltage outputs. the dac output voltage can be calculated by the follow- ing equation: v outx = v ref ? t pwhx /t perx where v ref is 2.5 v in internal reference mode or the ref pin voltage in external reference mode, t pwhx is the pulse width of the preceding in x period and t perx is the time between the two most recent in x rising edges. idlsel (pin 4): idle mode select input. connect idlsel to gnd or v cc to select the behavior of the dac output when there has been no rising edge on the pwm input for more than the idle mode timeout delay t 3 ( nominal delay is 60 ms). available idle mode states are power-down with high impedance output, hold previous state, zero-scale or full-scale. this pin also selects the initial state of the dac outputs following a power-on reset. iov cc (pin 5): i/o supply voltage input. 1.71v iov cc 5.5v. bypass to gnd with a 0.1f capacitor. gnd (pins 6, 12): ground. pd (pin 7): active-low power-down input. connect pd to gnd to place the part in power-down with a typical supply current of <1a . connect pd to iov cc for normal operation. in a , in b ( pins 9, 8): pwm inputs. apply a pulse-width modulated input frequency between 30 hz and 6.25khz (12-bit), 25khz (10- bit) or 100khz (8- bit). after each in x rising edge, the part calculates the duty cycle based upon the pulse width and period and updates dac channel v outx . logic levels are referenced to iov cc . refsel ( pin 11): reference select input. connect refsel to gnd to select internal reference mode. connect refsel to v cc to select external reference mode. ref (pin 10): reference voltage input or output. when refsel is connected to v cc , ref is an input (1v v ref v cc ) where the voltage supplied sets the full-scale dac output voltage. when refsel is connected to gnd, the 10ppm/c, 1.25 v internal reference ( half full-scale) is available at the pin. this output may be bypassed to gnd with up to 10 f and must be buffered when driving external dc load current. b lock diagra m 2644 bd pwm to binary conversion internal reference pwm to binary conversion dac a v ref dac b v outb in b in a pd idlsel iov cc gnd v outa v cc refsel ref gnd switch 5 4 7 9 8 12 6 3 2 1 10 11 ltc 2644 2644fa for more information www.linear.com/ltc2644
12 ti m ing diagra ms figure 1a. figure 1b. sample/hold operation (idlsel = v cc ) figure 1c. transparent operation (idlsel = gnd) 2644 td01a t per t 3 t pwl v out = (t pwh /t per ) ? v ref t pwh idle state in x v outx t 4 t s 2644 td01b t per1 t pwl < t 3 t hold1 > t 3 t pwh2 t per2 t pwh1 sample #1 hold #1 v out1 = (t pwh1 /t per1 )*v ref v out2 = (t pwh2 /t per2 )*v ref sample #2 hold #2 in x v outx t 4 t 4 2644 td01c t per1 t idle(low) t 3 t per2 t idle(high) t 3 t pwh1 t pwh2 sample #1 v out1 = (t pwh1 /t per1 ) ? v ref v out2 = (t pwh2 /t per2 ) ? v ref v out = gnd idle state timeout low idle state timeout high v out = v ref sample #2 in x v outx t 4 t 4 ltc 2644 2644fa for more information www.linear.com/ltc2644
13 o pera t ion the ltc2644 is a family of dual pwm input, voltage output dacs in a 12- lead msop package. the part measures the pulse width and period of the pwm inputs and updates each dac output after the corresponding pwm input rising edge. each dac can operate rail-to-rail using an external reference, or with a 2.5 v full-scale voltage using an integrated reference. three resolutions (12-, 10-, and 8-bit) are available. pwm -to-voltage conversion the ltc2644 converts a pwm input to an accurate, stable, buffered voltage without the latency, slow settling, and high- value passive components required for discrete solutions. the pwm input pins (in x ) accept frequencies from 30hz up to 6.25khz (12-bit), 25khz (10- bit), or 100khz (8-bit). the duty cycle is calculated after each pwm input rising edge based upon the previous high and low pulse width. the resulting digital dac code k is calculated as: k = 2 n ? t pwhx / t perx where t pwhx is the pulse width of the preceding in x period and t perx is the time between the two most recent in x rising edges. the digital-to-analog transfer function is: v out(ideal) = k 2 n ? ? ? ? ? ? v ref , for k = 0 to 2 n C 1 where n is the resolution, v ref is 2.5 v for internal reference mode or the ref pin voltage for external reference mode. dac update timing the update for dac output v outx occurs following each rising edge input on in x (figure 1 a). delay t s is the delay from an in x rising edge to the v outx settled output voltage corresponding to the previous periods duty cycle. delay t s is composed of the computational cycle delay (t 4 ) and the actual settling of the output dac. the pwm -to-binary, internal computational cycle begins immediately following the in x rising edge. the computational cycle is completed after delay t 4 and the dac output v outx is updated. the dac output typically settles to 12- bit accuracy within 8 s from the in x rising edge. pwm input idle mode selection when no pwm input rising edge is received for more than the idle mode timeout delay t 3 ( nominal delay is 60ms), the dac output enters an idle mode state which can be configured by connecting idlsel to gnd or v cc accord- ing to table 1 below. note that these pins also control the initial state of the dacs after power-on reset. table 1. power-on reset and idle mode states idlsel power-on reset in x idle low in x idle hi gnd zero-scale zero-scale full-scale v cc power-down hi-z power-down hi-z hold transparent operation for applications in which the pwm input duty cycle may be 0% or 100%, connect idlsel to gnd to select trans- parent operation, in which case an idle low input sets the dac to zero-scale or an idle high input sets the dac to full-scale. figure 1c illustrates the timing for transparent operation. any pair of pwm input rising edges separated by less than the idle mode timeout delay t 3 (50 ms mini- mum) will cause the dac code to be updated following the second rising edge. note that an idle high input state may be followed by an idle low input state. sample/hold operation the ltc2644 has the capability to sample the pulse- width/ period and hold the corresponding voltage level indefinitely. unlike analog filter implementations which require the pwm input to run continuously, the ltc2644 may operate with a discontinuous pwm input. connect idlsel to v cc to select sample/hold operation, in which a single pair of rising edges is sufficient to update the dac, and the dac code retains its previous value when the pw m input idles high. figure 1 b illustrates correct timing for ltc 2644 2644fa for more information www.linear.com/ltc2644
14 o pera t ion sample/ hold operations. any pair of rising edges separated by less than the idle timeout delay t 3 (50 ms minimum) will cause the dac code to be updated. any pair of rising edges separated by more than t 3 (70 ms maximum) will be ignored and the dac code will retain its previous value. note that after power-on-reset or when in x idles low, the dac will power down with a high impedance output. short in x period operation the accuracy of the pwm to voltage conversion is guar- anteed for in x input frequencies up to 6.25 khz (12-bit), 25khz (10- bit) or 100khz (8- bit). faster in x input fre- quencies will proportionally decrease the resolution and accuracy of the analog output. for in x input periods of less than the computational delay t 4 (nominally 3.2 s), the dac update will be skipped and the dac code will retain its previous value. short in x pulse-width operation provide in x input high and low pulse widths greater than t pwh and t pwl to ensure that the dac output is updated after every in x rising edge. high going pulses narrower than t pwh will cause the dac code to be calculated as zero-scale, and low going pulses narrower than t pwl will cause the dac code to be calculated as full-scale. for much narrower pulse widths of only a few nanoseconds, the input edge may not be recognized, in which case the dac update will be skipped entirely and the dac code will retain its previous value. power-on reset the ltc2644 resets the output to a known state when power is first applied, making system initialization con- sistent and repeatable. connect the idlsel pin to gnd or v cc according to table 1 to cause the dacs to initialize to zero-scale or with the device powered down and the dac outputs high impedance. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2644 contains circuitry to reduce the power-on glitch when zero-scale reset is selected: the analog output typically rises less than 5 mv above zero-scale during power on if the power supply is ramped to 5 v in 1 ms or more. in general, the glitch amplitude decreases as the power sup - ply ramp time is increased. reference modes for applications where an accurate external reference is not available, nor desirable due to limited space, the ltc2644 has a user- selectable, integrated reference. internal reference mode can be selected by connecting the refsel pin to gnd. the 10ppm/c , 1.25 v internal reference is available at the ref pin. this voltage is internally amplified by 2 x to provide a 2.5 v full-scale dac output voltage range. add- ing bypass capacitance to the ref pin will improve noise performance ; 0.1 f is recommended, and up to 10 f can be driven without oscillation. the ref output must be buffered when driving an external dc load current. alternatively, the dac can operate in external reference mode by connecting the refsel pin to v cc . in this mode, an input voltage supplied externally to the ref pin provides the reference (1v v ref v cc ) and the supply current is reduced. in this mode the full-scale dac output voltage is equal to the voltage at the ref pin. power-down mode for power constrained applications, power-down mode can be used to reduce the supply current whenever less than two dac outputs are needed. when in power-down mode, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. ltc 2644 2644fa for more information www.linear.com/ltc2644
15 o pera t ion if idlsel is connected to v cc , either or both channels can be powered down by keeping the pwm input(s) (in a /in b ) low for the idle mode timeout delay t 3 . the in- tegrated reference is automatically powered down when external reference mode is selected or when both dac channels are powered down. in addition, both dac chan - nels and the integrated reference can be powered down by pulling the pd pin low. when the integrated reference is powered down, the ref pin becomes high impedance (typically > 1g). normal operating current resumes when pd returns high for transparent operation ( idlsel = gnd). for sample/ hold operation (idlsel = v cc ), the ltc2644 remains in full power-down until the first rising edge is received on any pwm input. any pair of pwm input rising edges separated by less than the idle mode timeout delay t 3 (50ms minimum) will cause the dac code to be updated. the dac output(s) will remain in hi-z until the channel is updated following the second rising pwm input edge. voltage output the ltc2644s integrated rail-to-rail amplifier has guar- anteed load regulation when sourcing or sinking up to 10ma at 5v, and 5ma at 3v. load regulation is a measure of the amplifiers ability to maintain the rated voltage accuracy over a wide range of load current. the measured change in output voltage per change in forced load current is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to . the amplifiers dc output imped - ance is 0.1 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50 typical channel resistance of the output devices (e.g., when sinking 1ma, the minimum output voltage is 50 ? 1 ma, or 50 mv). see the graph headroom at rails vs output current in the typical performance character - istics section. the amplifier is stable driving capacitive loads of up to 500pf. rail-to-rail output considerations in any rail- to- rail voltage output device, the output is limited to voltages within the supply range. since the analog output of the dac cannot go below ground, it may limit the lowest codes reachable as shown in figure 2 b. similarly, limiting can occur near full-scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error ( fse) is positive, the output for the highest codes limits at v cc , as shown in figure 2 c. no full-scale limiting will occur if v ref is less than v cc Cfse. offset and linearity are defined and tested over the region of the dac transfer function where no output limiting can occur. board layout the pc board should have separate areas for the analog and digital sections of the circuit. a single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. this keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. the resistance from the ltc2644 gnd pin to the ground plane should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.1). note that the ltc2644 is no more susceptible to this effect than any other parts of this type; on the con - trary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. ltc 2644 2644fa for more information www.linear.com/ltc2644
16 o pera t ion figure 2. effects of rail-to-rail operation on a dac transfer curve (shown for 12 bits). (a) overall t ransfer function (b) effect of negative offset for codes near zero (c) effect of positive full-scale error for codes near full-scale 2645 f02 input code (b) output voltage negative offset 0v 0v 2048 0 4095 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse another technique for minimizing errors is to use a sepa- rate power ground return trace on another board layer. the trace should run between the point where the power supply is connected to the board and the dac ground pin. thus the dac ground pin becomes the common point for analog ground, digital ground, and power ground. when the ltc2644 is sinking large currents, this current flows out of the ground pin and directly into the power ground trace without affecting the analog ground plane voltage. it is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. when doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. ltc 2644 2644fa for more information www.linear.com/ltc2644
17 typical a pplica t ions figure 3. analog control voltage with pwm transmission to dac control voltage output 2644 f03 pwm to binary ltc2644 -12 isolation barrier ps9851-1 pwm to binary dac a ref iov cc v cc idlsel refsel dac b v outb v outb = hi-z gnd v outa dac control voltage output (0v to v ref ) in b in a pd 2.7v to 5.5v 5v ext input: 1v to v cc c3 0.1f LTC6992 r set 50k 2.25v to 5.5v mod analog pwm duty cycle control (0v to 1v) out gnd v + set div c1 0.1f c4 0.1f c2 0.1f ltc 2644 2644fa for more information www.linear.com/ltc2644
18 p ackage descrip t ion msop (ms12) 0213 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 11 10 9 8 7 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) ms package 12-lead plastic msop (reference ltc dwg # 05-08-1668 rev a) please refer to http://www .linear.com/product/ltc2644#packaging for the most recent package drawings. ltc 2644 2644fa for more information www.linear.com/ltc2644
19 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 02/17 corrected v out(ideal) equation 13 ltc 2644 2644fa for more information www.linear.com/ltc2644
20 ? linear technology corporation 2014 lt 0217 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2644 r ela t e d p ar t s typical a pplica t ion part number description comments ltc2645 quad 12-/10-/8-bit pwm to v out dacs with 10ppm/c reference zero latency bus update, 100khz to 30hz input frequency, 2.5lsb inl, 2.7v to 5.5v supply range, 16-lead msop package lt ? 1991 precision, 100a gain selectable amplifier gain accuracy of 0.04%, gains from C13 to 14, 100a precision op amp lt1469-2 dual 200mhz, 30v/s 16-bit accurate op amp 200mhz gain bandwidth, 125v offset, 30v/s slew rate precision op amp ltc2055 dual micropower zero-drift op amp 2.7v minimum supply voltage, 150a supply current per amplifier, zero-drift op amp ltc 6992 t imer blox: voltage-controlled pulse width modulator ( pwm ) 3.8hz to 1mhz output frequency range, 0v to 1v analog input, < 1.7% maximum frequency error ltc2632/ltc2633 dual 12-/10-/8-bit spi/i 2 c v out dacs with 10ppm/c reference 2.5lsb inl, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, 8-lead thinsot? package figure 4. voltage margining application with ltc3850 (3.3v 10%) sw1 bg1 pgnd i th1 sense1 + mode/pllin run1 sense1 ? v fb1 500khz tkss1 i lm v in intv cc pgood tg1 0.1f 1nf 0.1f 2.2k 100k 10k sgnd 10k 0.008k 2.2h ltc3850euf 2645 f04 freq boost1 0.1f cmdsh-3 rjk0305dpb rjk0301dpb 10nf 1nf 3.32k 10k 1nf 10k 100pf 4.7f v in 6.5v to 14v v out 3.3v 10% 20k 15pf 63.4k 0.1f pwm to binary ltc2644 -12 pwm to binary dac a ref iov cc v cc idlsel refsel dac b v outb v outb = hi-z for no margining, keep in a low. (v outa = hi-z) to margin 10% high, set in a duty cycle to 1/4096 (v outa = 0v) to margin 10% low, set in a duty cycle to 2621/4096 (v outa = 1.6v) gnd v outa in b in a pd 5v c3 0.1f c4 0.1f 10k 143k ltc 2644 2644fa for more information www.linear.com/ltc2644

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